The present invention relates to a semiconductor circuit device, and in particular relates to a technology, being effective when applied onto a MOS circuit which is operated at a plural number of operating speeds, or when applied onto a MOS circuit on which high speed operation is required.
Due to a search made after accomplishing the present invention, though will be explained later, it appears that there is known Japanese Patent Laying-Open No. 11-122047 (1999) (hereinafter, prior art 1), as a prior art seeming to be relevant thereto. In the Patent Laying-Open of the prior art 1, for the purpose of reducing current consumption without deteriorating the process performance or property thereof, a voltage level of a back gate voltage, which is applied to a back gate of a MOS transistor contained within an interior circuit, is supplied by selecting an output voltage from a voltage generator for generating a plurality of voltages, being different in the voltage levels thereof, depending upon an operation mode from a mode signal, thereby changing a threshold level of the MOS transistor. Also, though being different from the above-mentioned prior art 1 in a premise thereof, an invention was already made by the inventors of the present patent application, for compensating process fluctuation of the MOS transistors by means of a substrate bias controlling scheme, and was proposed in Japanese Patent Laying-Open No. 8-274620 (1996) (hereinafter, prior art 2).
In the prior art 1 mentioned above, in order to change the back gate voltage of the MOS transistor for the purpose of a low electric power consumption therein, there are provided a number of the voltage generators, being corresponding to those. As such the voltage generators, for example, a charge pump circuit is used, as shown in attached FIG. 9 of the Patent Laying-Open mentioned above, in particular, in a case of producing a negative back gate voltage therefrom. This charge pump circuit is so-called a DC-DC. converter, however a voltage conversion efficiency is lower, then the power consumption thereof comes to be relative large.
In the prior art 1 mentioned above, when having the plural number of operation modes, as was mentioned in the above, it comes to be large in circuit scale (i.e., the number of transistors in the circuit), due to the necessity of the number of the voltage generators corresponding to them, and in such one, in which the back gates are generated corresponding to the plural number of the operation modes, as was mentioned in the above, on the contrary to that the necessary back gate is only one (1) in one (1) operation mode, there is a problem that wasteful consumption of current occurs for generating the back gate voltages which are not used. Then, it is sufficient that only the voltage generator corresponding thereto is operated when having only one (1) operation mode, while stopping the operation of the voltage generators corresponding to the other back gate voltages, however in such the case, it follows a victim of loosing a responsibility in changing over the operation modes.
For dissolving such the problem in the prior art 1 mentioned above, combining the prior art 2 which was invented previously with it, but from a view point being totally different from that, by the inventors of the present patent application, there is achieved a development of a semiconductor integrated circuit device constructed with CMOS components, with which not only a simplification in circuit and a low electric power thereof can be achieved in common, but also be able to cope with the process fluctuation, thereby enabling a great improvement in the yield of products, and/or a semiconductor integrated circuit device constructed with MOS components, with which can be achieved a high speed, while maintaining an improvements in the yield of products and in the reliability thereof, as well.
An object of the present invention is to provide a semiconductor integrated circuit device for achieving improvements on the low electric power and/or the yield of products, while reducing the scale of circuits (i.e., the number of transistors in the circuit). Other object of the present invention, in addition to the above, is to provide a semiconductor integrated circuit device for achieving an improvement in a usability thereof. A further other object of the present invention is to provide a semiconductor integrated circuit device for achieving a high speed while maintaining the improvements in the yield of products and/or the reliability thereof. And, a further other object of the present invention, in addition to the above, is to provide a semiconductor integrated circuit device, being adapted or suitable to controllability and/or miniaturization of elements or devices. Those objects of the present invention mentioned above and other(s), as well as the novel feature(s) thereof, will be apparent from the description of the present specification and the drawings attached thereto.
Briefly explaining on an outline of a representative one of the present invention disclosed in the present application, it is as follows. Namely, in a semiconductor integrated circuit device, according to the present invention, for a main circuit being constructed with CMOS are provided a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof, and a substrate bias controller for supplying corresponding substrate bias voltages to semiconductor regions, where a P-channel type MOSFET and a N-channel type MOSFET are formed for constructing the main circuit and the speed monitor circuit mentioned above, respectively, wherein the substrate bias voltages are formed by means of the substrate bias controller mentioned above, so that a speed signal to be set at corresponding one of plural kinds of the operating speeds and the speed signal mentioned above are coincident with.
Briefly explaining on an outline of other representative one of the present invention disclosed in the present application, it is as follows. Namely, in a semiconductor integrated circuit device, according to the present invention, for a main circuit being constructed with CMOS are provided a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof, and a substrate bias controller, thereby controlling substrate bias of the main circuit and the speed monitor circuit mentioned above, so that the speed signal being set corresponding to the plural kinds of operating speeds and the speed signal mentioned above are coincident with, by means of the substrate bias controller mentioned above.
Briefly explaining on an outline of further other representative one of the present invention disclosed in the present application, it is as follows. Namely, in a semiconductor integrated circuit device, according to the present invention, while supplying a positive bias voltage to the semiconductor regions where MOSFET is formed for constructing the main circuit, by means of the substrate bias circuit, there is provided a current limiting circuit for limiting the current supplied to the above-mentioned semiconductor region, in response to the substrate current flowing between the semiconductor region and the source thereof.